63.10.1 FLEXCOM Mode Register
| Name: | FLEX_MR |
| Offset: | 0x000 |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OPMODE[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 1 | |||||||
Bits 1:0 – OPMODE[1:0] FLEXCOM Operating Mode
| Value | Name | Description |
|---|---|---|
| 0 | NO_COM | No communication |
| 1 | USART | All
UART-related protocols are selected (RS232, RS485, IrDA, ISO7816, LIN,) SPI/TWI-related registers are not accessible and have no impact on IOs. |
| 2 | SPI | SPI
operating mode is selected. USART/TWI related registers are not accessible and have no impact on IOs. |
| 3 | TWI | All
TWI-related protocols are selected (TWI, SMBus). USART/SPI-related registers are not accessible and have no impact on IOs. |