This register reads ‘0’ if
the FIFO is disabled (see FLEX_TWI_CR to enable/disable the internal
FIFO).
Name:
FLEX_TWI_FIMR
Offset:
0x66C
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
RXFPTEF
TXFPTEF
RXFTHF
RXFFF
RXFEF
TXFTHF
TXFFF
TXFEF
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit 7 – RXFPTEF RXFPTEF Interrupt Mask
Bit 6 – TXFPTEF TXFPTEF Interrupt Mask
Bit 5 – RXFTHF RXFTHF Interrupt Mask
Bit 4 – RXFFF RXFFF Interrupt Mask
Bit 3 – RXFEF RXFEF Interrupt Mask
Bit 2 – TXFTHF TXFTHF Interrupt Mask
Bit 1 – TXFFF TXFFF Interrupt Mask
Bit 0 – TXFEF TXFEF Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
