63.10.34 USART FIFO Event Status Register
| Name: | FLEX_US_FESR |
| Offset: | 0x2B4 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RXFTHF2 | TXFLOCK | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXFPTEF | TXFPTEF | RXFTHF | RXFFF | RXFEF | TXFTHF | TXFFF | TXFEF | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 9 – RXFTHF2 Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)
| Value | Description |
|---|---|
| 0 | Number of unread data in Receive FIFO is above RXFTHRES threshold. |
| 1 | Number of unread data in Receive FIFO has reached RXFTHRES2 threshold since the last RSTSTA command was issued. |
Bit 8 – TXFLOCK Transmit FIFO Lock
| Value | Description |
|---|---|
| 0 | The Transmit FIFO is not locked. |
| 1 | The Transmit FIFO is locked. |
Bit 7 – RXFPTEF Receive FIFO Pointer Error Flag
See 63.7.11.9 FIFO Pointer Error for details.
| Value | Description |
|---|---|
| 0 | No Receive FIFO pointer occurred. |
| 1 | Receive FIFO pointer error occurred. Receiver must be reset. |
Bit 6 – TXFPTEF Transmit FIFO Pointer Error Flag
See 63.7.11.9 FIFO Pointer Error for details.
| Value | Description |
|---|---|
| 0 | No Transmit FIFO pointer occurred. |
| 1 | Transmit FIFO pointer error occurred. Transceiver must be reset. |
Bit 5 – RXFTHF Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
| Value | Description |
|---|---|
| 0 | Number of unread data in Receive FIFO is below RXFTHRES threshold. |
| 1 | Number of unread data in Receive FIFO has reached RXFTHRES threshold since the last RSTSTA command was issued. |
Bit 4 – RXFFF Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
| Value | Description |
|---|---|
| 0 | Receive FIFO is not empty. |
| 1 | Receive FIFO has been filled since the last RSTSTA command was issued. |
Bit 3 – RXFEF Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
| Value | Description |
|---|---|
| 0 | Receive FIFO is not empty. |
| 1 | Receive FIFO has been emptied since the last RSTSTA command was issued. |
Bit 2 – TXFTHF Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
| Value | Description |
|---|---|
| 0 | Number of data in Transmit FIFO is above TXFTHRES threshold. |
| 1 | Number of data in Transmit FIFO has reached TXFTHRES threshold since the last RSTSTA command was issued. |
Bit 1 – TXFFF Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
| Value | Description |
|---|---|
| 0 | Transmit FIFO is not full. |
| 1 | Transmit FIFO has been filled since the last RSTSTA command was issued. |
Bit 0 – TXFEF Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
| Value | Description |
|---|---|
| 0 | Transmit FIFO is not empty. |
| 1 | Transmit FIFO has been emptied since the last RSTSTA command was issued. |