The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
FLEX_SPI_IMR
Offset:
0x41C
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
RXFPTEF
TXFPTEF
RXFTHF
RXFFF
RXFEF
TXFTHF
TXFFF
TXFEF
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
SFERR
CMP
UNDES
TXEMPTY
NSSR
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OVRES
MODF
TDRE
RDRF
Access
R
R
R
R
Reset
0
0
0
0
Bit 31 – RXFPTEF RXFPTEF Interrupt Mask
Bit 30 – TXFPTEF TXFPTEF Interrupt Mask
Bit 29 – RXFTHF RXFTHF Interrupt Mask
Bit 28 – RXFFF RXFFF Interrupt Mask
Bit 27 – RXFEF RXFEF Interrupt Mask
Bit 26 – TXFTHF TXFTHF Interrupt Mask
Bit 25 – TXFFF TXFFF Interrupt Mask
Bit 24 – TXFEF TXFEF Interrupt Mask
Bit 12 – SFERR Client Mode Frame Error Interrupt
Mask
Bit 11 – CMP Comparison Interrupt Mask
Bit 10 – UNDES Underrun Error Interrupt Mask
Bit 9 – TXEMPTY Transmission Registers Empty Mask
Bit 8 – NSSR NSS Rising Interrupt Mask
Bit 3 – OVRES Overrun Error Interrupt Mask
Bit 2 – MODF Mode Fault Error Interrupt Mask
Bit 1 – TDRE SPI Transmit Data Register Empty Interrupt Mask
Bit 0 – RDRF Receive Data Register Full Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
