63.10.43 SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit)

To write multi-data, the FIFO must be enabled (FLEX_SPI_CR.FIFOEN=1) and FLEX_SPI_MR.PS=0. The access type (byte, halfword or word) determines the number of data written in a single access (1 or 2), see SPI Single Data Access for details.

Name: FLEX_SPI_TDR (FIFO_MULTI_DATA)
Offset: 0x40C
Reset: 
Property: Write-only

Bit 3130292827262524 
 TD1[15:8] 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 TD1[7:0] 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 TD0[15:8] 
Access WWWWWWWW 
Reset  
Bit 76543210 
 TD0[7:0] 
Access WWWWWWWW 
Reset  

Bits 0:15, 16:31 – TDx Transmit Data

Next data to write in the Transmit FIFO. Information to be transmitted must be written to this register in a right-justified format.