The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Name:
FLEX_TWI_IMR
Offset:
0x62C
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
SMBHHM
SMBDAM
PECERR
TOUT
MCACK
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TXBUFE
RXBUFF
ENDTX
ENDRX
EOSACC
SCL_WS
ARBLST
NACK
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
UNRE
OVRE
GACC
SVACC
TXRDY
RXRDY
TXCOMP
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
Bit 21 – SMBHHM SMBus Host Header Address Match Interrupt Mask
Bit 20 – SMBDAM SMBus Default Address Match Interrupt Mask
Bit 19 – PECERR PEC Error Interrupt Mask
Bit 18 – TOUT Timeout Error Interrupt Mask
Bit 16 – MCACK Host Code Acknowledge Interrupt
Mask
Bit 15 – TXBUFE Transmit Buffer Empty Interrupt Mask
Bit 14 – RXBUFF Receive Buffer Full Interrupt Mask
Bit 13 – ENDTX End of Transmit Buffer Interrupt Mask
Bit 12 – ENDRX End of Receive Buffer Interrupt Mask
Bit 11 – EOSACC End Of Client Access Interrupt
Mask
Bit 10 – SCL_WS Clock Wait State Interrupt Mask
Bit 9 – ARBLST Arbitration Lost Interrupt Mask
Bit 8 – NACK Not Acknowledge Interrupt Mask
Bit 7 – UNRE Underrun Error Interrupt Mask
Bit 6 – OVRE Overrun Error Interrupt Mask
Bit 5 – GACC General Call Access Interrupt Mask
Bit 4 – SVACC Client Access Interrupt
Mask
Bit 2 – TXRDY Transmit Holding Register Ready Interrupt Mask
Bit 1 – RXRDY Receive Holding Register Ready Interrupt Mask
Bit 0 – TXCOMP Transmission Completed Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
