63.10.38 SPI Mode Register

This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time ensures chip selects do not overlap and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is ≤ 6, six peripheral clock periods are inserted by default.

Otherwise, the following equations determine the delay:

If FLEX_SPI_MR.BRSRCCLK = 0: DLYBCS = Delay Between Chip Selects × f_{peripheral clock}

If FLEX_SPI_MR.BRSRCCLK = 1: DLYBCS = Delay Between Chip Selects × f_GCLK

This field is only used if fixed peripheral select is active (PS = 0).

If PCSDEC = 0:

PCS = xxx0 NPCS[3:0] = 1110

PCS = xx01 NPCS[3:0] = 1101

PCS = x011 NPCS[3:0] = 1011

PCS = 0111 NPCS[3:0] = 0111

PCS = 1111 forbidden (no peripheral is selected)

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] output signals = PCS

LLB controls the local loopback on the data shift register for testing in Host mode only (MISO is internally connected on MOSI).

When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four NPCS lines using an external 4- to 16-bit decoder. The Chip Select registers define the characteristics of the 15 chip selects, with the following rules:

FLEX_SPI_CSR0 defines peripheral chip select signals 0 to 3.

FLEX_SPI_CSR1 defines peripheral chip select signals 4 to 7.

FLEX_SPI_CSR2 defines peripheral chip select signals 8 to 11.

FLEX_SPI_CSR3 defines peripheral chip select signals 12 to 14.