63.10.38 SPI Mode Register

This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register.

Name: FLEX_SPI_MR
Offset: 0x404
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 DLYBCS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
     PCS[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
    CMPMODE     
Access R/W 
Reset 0 
Bit 76543210 
 LLB WDRBTMODFDISBRSRCCLKPCSDECPSMSTR 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 31:24 – DLYBCS[7:0] Delay Between Chip Selects

This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time ensures chip selects do not overlap and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is ≤ 6, six peripheral clock periods are inserted by default.

Otherwise, the following equations determine the delay:

If FLEX_SPI_MR.BRSRCCLK = 0: DLYBCS = Delay Between Chip Selects × fperipheral clock

If FLEX_SPI_MR.BRSRCCLK = 1: DLYBCS = Delay Between Chip Selects × fGCLK

Bits 19:16 – PCS[3:0] Peripheral Chip Select

This field is only used if fixed peripheral select is active (PS = 0).

If PCSDEC = 0:

PCS = xxx0 NPCS[3:0] = 1110

PCS = xx01 NPCS[3:0] = 1101

PCS = x011 NPCS[3:0] = 1011

PCS = 0111 NPCS[3:0] = 0111

PCS = 1111 forbidden (no peripheral is selected)

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] output signals = PCS

Bit 12 – CMPMODE Comparison Mode

ValueNameDescription
0 FLAG_ONLY Any character is received and comparison function drives CMP flag.
1 START_CONDITION Comparison condition must be met to start reception of all incoming characters until REQCLR is set.

Bit 7 – LLB Local Loopback Enable

LLB controls the local loopback on the data shift register for testing in Host mode only (MISO is internally connected on MOSI).

ValueDescription
0 Local loopback path disabled.
1 Local loopback path enabled.

Bit 5 – WDRBT Wait Data Read Before Transfer

ValueDescription
0 No Effect. In Host mode, a transfer can be initiated regardless of the FLEX_SPI_RDR state.
1 In Host mode, a transfer can start only if FLEX_SPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.

Bit 4 – MODFDIS Mode Fault Detection

ValueDescription
0 Mode fault detection is enabled.
1 Mode fault detection is disabled.

Bit 3 – BRSRCCLK Bit Rate Source Clock

If the bit BRSRCCLK = 1, the FLEX_US_CSRx.SCBR field must be programmed with a value greater than 1.
ValueNameDescription
0 PERIPH_CLK The peripheral clock is the source clock for the bit rate generation.
1 GCLK GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.

Bit 2 – PCSDEC Chip Select Decode

When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four NPCS lines using an external 4- to 16-bit decoder. The Chip Select registers define the characteristics of the 15 chip selects, with the following rules:

FLEX_SPI_CSR0 defines peripheral chip select signals 0 to 3.

FLEX_SPI_CSR1 defines peripheral chip select signals 4 to 7.

FLEX_SPI_CSR2 defines peripheral chip select signals 8 to 11.

FLEX_SPI_CSR3 defines peripheral chip select signals 12 to 14.

ValueDescription
0 The chip selects are directly connected to a peripheral device.
1 The four NPCS chip select lines are connected to a 4- to 16-bit decoder.

Bit 1 – PS Peripheral Select

ValueDescription
0 Fixed Peripheral Select
1 Variable Peripheral Select

Bit 0 – MSTR Host/Client Mode

ValueDescription
0 SPI is in Client mode.
1 SPI is in Host mode.