63.10.73 TWI High-Speed Clock Waveform Generator Register

This register can only be written if the WPEN bit is cleared in the TWI Write Protection Mode Register.

FLEX_TWI_HSCWGR is only used in High-Speed Host mode.

Name:	FLEX_TWI_HSCWGR
Offset:	0x648
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
						HSCKDIV[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8
	HSCHDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	HSCLDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 18:16 – HSCKDIV[2:0] High-Speed Clock Divider

The CKDIV is used to increase both SCL high and low periods.

Bits 15:8 – HSCHDIV[7:0] High-Speed Clock High Divider

The SCL high period is defined as follows:

If BRSRCCLK = 0: CHDIV = ((t_high/t_{peripheralclock}) - 3)/2^CKDIV
If BRSRCCLK = 1: CHDIV = (t_high/t_{ext_ck})/2^CKDIV

Bits 7:0 – HSCLDIV[7:0] High-Speed Clock Low Divider

The SCL low period is defined as follows:

If BRSRCCLK = 0: CLDIV = ((t_low/t_{peripheralclock}) - 3)/2^CKDIV
If BRSRCCLK = 1: CLDIV = (t_low/t_{ext_ck})/2^CKDIV

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