63.10.40 SPI Receive Data Register (FIFO Multiple Data, 8-bit)

To read multi-data, the FIFO must be enabled (FLEX_SPI_CR.FIFOEN=1) and FLEX_SPI_MR.PS=0. The access type (byte, halfword or word) determines the number of data written in a single access (1, 2 or 4), see SPI Multiple Data Access for details.

Name: FLEX_SPI_RDR (FIFO_MULTI_DATA_8)
Offset: 0x408
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 RD3[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 RD2[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 RD1[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 RD0[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 0:7, 8:15, 16:23, 24:31 – RDx Receive Data

First unread data in the Receive FIFO. Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero.