63.10.50 SPI FIFO Level Register

This register reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).
Name: FLEX_SPI_FLR
Offset: 0x444
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   RXFL[5:0] 
Access RRRRRR 
Reset 000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   TXFL[5:0] 
Access RRRRRR 
Reset 000000 

Bits 21:16 – RXFL[5:0] Receive FIFO Level

ValueDescription
0

There is no unread data in the Receive FIFO.
1–32

Indicates the number of unread data in the Receive FIFO.

Bits 5:0 – TXFL[5:0] Transmit FIFO Level

ValueDescription
0

There is no data in the Transmit FIFO.
1–32

Indicates the number of data in the Transmit FIFO.