42.6.41 CSI2DC Data Pipe Interrupt Enable Register
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Name:
CSI2DC_DPIER
Offset:
0xC8
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
LTE
STE
DATOVF
RXOVF1
RXOVF0
RXRDY1
RXRDY0
CAPTURE
Access
W
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
–
Bit 7 – LTE Longer Than Expected Packet Received Interrupt Enable Bit
Bit 6 – STE Shorter Than Expected Packet Received Interrupt Enable
Bit 5 – DATOVF Data Pipe Overflow Interrupt Enable
Bit 4 – RXOVF1 Bank 1, Packet Overflow Interrupt Enable
Bit 3 – RXOVF0 Bank 0, Packet Overflow Interrupt Enable
Bit 2 – RXRDY1 Bank 1, Packet Received Interrupt Enable
Bit 1 – RXRDY0 Bank 0, Packet Received Interrupt Enable
Bit 0 – CAPTURE Data Pipe Capture Done Interrupt Enable
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