42.6.8 CSI2DC SSP Interrupt Enable Register

Name: CSI2DC_SSPIER
Offset: 0x1C
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     RE[3:0] 
Access WWWW 
Reset  
Bit 15141312111098 
 LE[3:0]LS[3:0] 
Access WWWWWWWW 
Reset  
Bit 76543210 
 FE[3:0]FS[3:0] 
Access WWWWWWWW 
Reset  

Bits 19:16 – RE[3:0] Reserved Short Packet Interrupt Enable

ValueDescription
0

No effect.

1

Setting a bit at position i in the RE field will set the interrupt mask bit for virtual channel i, and this virtual channel can generate an interrupt when a Reserved Short Packet is detected.

Bits 15:12 – LE[3:0] Line End Interrupt Enable

ValueDescription
0

No effect.

1

Setting a bit at position i in the LE field will set the interrupt mask bit for virtual channel i, and this virtual channel can generate an interrupt when a Line End is detected. Line Synchronization packets are optional.

Bits 11:8 – LS[3:0] Line Start Interrupt Enable

ValueDescription
0

No effect.

1

Setting a bit at position i in the LS field will set the interrupt mask bit for virtual channel i, and this virtual channel can generate an interrupt when a Line Start is detected. Line Synchronization packets are optional.

Bits 7:4 – FE[3:0] Frame End Interrupt Enable

ValueDescription
0

No effect.

1

Setting a bit at position i in the FE field will set the interrupt mask bit for virtual channel i, and this virtual channel can generate an interrupt when a Frame End is detected.

Bits 3:0 – FS[3:0] Frame Start Interrupt Enable

ValueDescription
0

No effect.

1

Setting a bit at position i in the FS field will set the interrupt mask bit for virtual channel i, and this virtual channel can generate an interrupt when a Frame Start is detected.