42.6.3 CSI2DC Global Status Register
| Name: | CSI2DC_GSR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ARSTIP | RSTIP | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 1 – ARSTIP Asynchronous Reset in Progress
This bit can be cleared only if the D-PHY clock is running.
| Value | Description |
|---|---|
| 0 | No reset in progress for the asynchronous domain. |
| 1 | Asynchronous domain is being reset. |
Bit 0 – RSTIP Reset in Progress
| Value | Description |
|---|---|
| 0 | No reset in progress for the synchronous domain. |
| 1 | Synchronous domain is being reset. |