42.6.40 CSI2DC Pipe Update Status Register
| Name: | CSI2DC_PUSR |
| Offset: | 0xC4 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SIP | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DP | VP | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 31 – SIP Synchronization In Progress
| Value | Description |
|---|---|
| 0 | No synchronization pending. |
| 1 | Synchronization across clock domain boundary is in progress. If the MIPI interface clock is gated, the synchronization procedure will wait for the first valid MIPI packet to activate the receiver clock. |
Bit 1 – DP Data Pipe Update
| Value | Description |
|---|---|
| 0 | No data pipe in progress. |
| 1 | Data pipe configuration is in progress. This bit is cleared at the next frame start packet if the virtual channel identifier matches the CSI2DC_DPCFG.VC field. |
Bit 0 – VP Video Pipe Update
| Value | Description |
|---|---|
| 0 | No video pipe in progress. |
| 1 | Video pipe configuration is in progress. This bit is cleared at the next frame start packet if the virtual channel identifier matches the CSI2DC_VPCFG.VC field. |