42.6.21 CSI2DC GSP Interrupt Disable Register
| Name: | CSI2DC_GSPIDR |
| Offset: | 0x60 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GSPERR[3:0] | GSPRDY[3:0] | ||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bits 7:4 – GSPERR[3:0] Generic Short Packet Error Interrupt Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Setting a bit at position i in the GSPERR field will clear the interrupt mask bit for virtual channel i. |
Bits 3:0 – GSPRDY[3:0] Generic Short Packet Ready Interrupt Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Setting a bit at position i in the GSPRDY field will clear the interrupt mask bit for virtual channel i. |