42.6.1 CSI2DC Global Configuration Register
| Name: | CSI2DC_GCFGR |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HLC[3:0] | SECDEDN | ULC | GPIOSEL | MIPIFRN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:4 – HLC[3:0] CSI2DC Output Waveform Inter-line Minimum Delay
Inserts a minimal delay of (HLC+1) clock cycles between each line.
Bit 3 – SECDEDN Single Error Correction Double Error Detection Enable
| Value | Description |
|---|---|
| 0 | Packet header error correction is activated. |
| 1 | Packet header error correction is disabled. |
Bit 2 – ULC Use Optional Line Packet Delimiter
| Value | Description |
|---|---|
| 0 | Line packets are not used to define the line boundary. |
| 1 | Line Start and Line End optional packets are used to activate and deactivate the line. |
Bit 1 – GPIOSEL GPIO Parallel Interface Selection
| Value | Description |
|---|---|
| 0 | The MIPI CSI-2 serial interface is activated. |
| 1 | The GPIO parallel interface is selected and internally routed to the Image Signal Processor. |
Bit 0 – MIPIFRN MIPI Interface Free Running Clock
| Value | Description |
|---|---|
| 0 | The sensor MIPI clock is free-running. |
| 1 | The sensor MIPI clock is gated. |