The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Setting a bit at position i in this field clears the interrupt mask bit for virtual channel i.
Name:
CSI2DC_SSPIDR
Offset:
0x20
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
RE[3:0]
Access
W
W
W
W
Reset
–
–
–
–
Bit
15
14
13
12
11
10
9
8
LE[3:0]
LS[3:0]
Access
W
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
FE[3:0]
FS[3:0]
Access
W
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
–
Bits 19:16 – RE[3:0] Reserved Short Packet Interrupt Disable
Bits 15:12 – LE[3:0] Line End Interrupt Disable
Bits 11:8 – LS[3:0] Line Start Interrupt Disable
Bits 7:4 – FE[3:0] Frame End Interrupt Disable
Bits 3:0 – FS[3:0] Frame Start Interrupt Disable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
