The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Setting a bit at position i in this field clears the interrupt mask bit for Virtual Channel i.
Name:
CSI2DC_GLPIDR
Offset:
0x80
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
RE[3:0]
EB[3:0]
Access
W
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
BL[3:0]
NU[3:0]
Access
W
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
–
Bits 15:12 – RE[3:0] Reserved Packet Interrupt Disable Bit
Bits 11:8 – EB[3:0] Embedded 8-bit Non-Image Data Interrupt Disable Bit
Bits 7:4 – BL[3:0] Blanking Data Interrupt Disable Bit
Bits 3:0 – NU[3:0] Null Interrupt Disable Bit
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