42.6.44 CSI2DC Data Pipe Interrupt Status Register
Name: | CSI2DC_DPISR |
Offset: | 0xD4 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
LTE | STE | DATOVF | RXOVF1 | RXOVF0 | RXRDY1 | RXRDY0 | CAPTURE | ||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – LTE Packet Longer Than Expected
Value | Description |
---|---|
0 | No LTE packet detected. |
1 | A packet has been received but the actual length is longer that the packet word count value. |
Bit 6 – STE Packet Shorter Than Expected
Value | Description |
---|---|
0 | No STE packet detected since the last clear operation of the register. |
1 | A packet has been received but the actual length is shorter that the packet word count value. |
Bit 5 – DATOVF Data Overflow
Value | Description |
---|---|
0 | No overflow detected since the last clear operation of the register. |
1 | Data overflow in the clock domain crossing FIFO. |
Bit 4 – RXOVF1 Bank 1 Overflow
Value | Description |
---|---|
0 | No overflow detected since the last clear operation of the register. |
1 | An overflow occurred in bank 1. |
Bit 3 – RXOVF0 Bank 0 Overflow
Value | Description |
---|---|
0 | No overflow detected since the last clear operation of the register. |
1 | An overflow occurred in bank 0. |
Bit 2 – RXRDY1 Bank 1 Packet Received
Value | Description |
---|---|
0 | No packet received in bank 1 since the last clear operation of the register. |
1 | A new packet has been captured in the data pipe. |
Bit 1 – RXRDY0 Bank 0 Packet Received
Value | Description |
---|---|
0 | No packet received in bank 0 since the last clear operation of the register. |
1 | A new packet has been captured in the data pipe. |
Bit 0 – CAPTURE Captured Frame
Value | Description |
---|---|
0 | No frame captured on the data pipe interface since the last clear operation of the register. |
1 | A new frame has been captured in the data pipe. |