42.6.6 CSI2DC Global Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is masked.

1: The corresponding interrupt is activated.

Name:	CSI2DC_GIMR
Offset:	0x14
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	DED	SEC	DP	VP	IDS	GLP	GSP	SSP
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – DED Double Error Detected Interrupt Disable Interrupt Mask

Bit 6 – SEC Single Error Corrected Interrupt Disable Interrupt Mask

Bit 5 – DP Data Pipe Interrupt Disable Interrupt Mask

Bit 4 – VP Video Pipe Interrupt Disable Interrupt Mask

Bit 3 – IDS Image Data Packet Snoop Controller Interrupt Mask

Bit 2 – GLP Generic Long Packet Interrupt Mask

Bit 1 – GSP Generic Short Packet Interrupt Mask

Bit 0 – SSP Synchronization Short Packet Interrupt Mask

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