42.6.42 CSI2DC Data Pipe Interrupt Disable Register
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name:
CSI2DC_DPIDR
Offset:
0xCC
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
LTE
STE
DATOVF
RXOVF1
RXOVF0
RXRDY1
RXRDY0
CAPTURE
Access
W
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
–
Bit 7 – LTE Longer Than Expected Packet Received Interrupt Disable
Bit 6 – STE Shorter Than Expected Packet Received Interrupt Disable
Bit 5 – DATOVF Data Pipe Overflow Interrupt Disable
Bit 4 – RXOVF1 Bank 1, Packet Overflow Interrupt Disable
Bit 3 – RXOVF0 Bank 0, Packet Overflow Interrupt Disable
Bit 2 – RXRDY1 Bank 1, Packet Received Interrupt Disable
Bit 1 – RXRDY0 Bank 0, Packet Received Interrupt Disable
Bit 0 – CAPTURE Data Pipe Capture Done Interrupt Disable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
