2.7.1.1 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports:
- 1 to 240 interrupts.
- A programmable priority level of 0-255 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
- Level and pulse detection of interrupt signals.
- Dynamic reprioritization of interrupts.
- Grouping of priority values into group priority and subpriority fields.
- Interrupt tail-chaining.
- An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is:
| Address | Name | Type | Required privilege | Reset value | See |
|---|---|---|---|---|---|
| 0xE000E100 - 0xE000E11C | NVIC_ISER0- NVIC_ISER7 | RW | Privileged | 0x00000000 | Interrupt Set-enable Registers |
| 0XE000E180- 0xE000E19C | NVIC_ICER0- NVIC_ICER7 | RW | Privileged | 0x00000000 | Interrupt Clear-enable Registers |
| 0XE000E200- 0xE000E21C | NVIC_ISPR0- NVIC_ISPR7 | RW | Privileged | 0x00000000 | Interrupt Set-pending Registers |
| 0XE000E280- 0xE000E29C | NVIC_ICPR0- NVIC_ICPR7 | RW | Privileged | 0x00000000 | Interrupt Clear-Pending Registers |
| 0xE000E300- 0xE000E31C | NVIC_IABR0- NVIC_IABR7 | RO | Privileged | 0x00000000 | Interrupt Active Bit Registers |
| 0xE000E400- 0xE000E4EF | NVIC_IPR0- NVIC_IPR59 | RW | Privileged | 0x00000000 | Interrupt Priority Registers |
| 0xE000EF00 | STIR | WO | Configurable 1 | 0x00000000 | Software Trigger Interrupt Register |
Note:
- See the register description for more information.