2.7.1.5 Interrupt Set-pending Registers

The NVIC_ISPR0-NVIC_ISPR7 registers force interrupts into the pending state, and show which interrupts are pending. See the register summary in Table 2-34 for the register attributes.

The bit assignments are:

Figure 2-21. ISPR Register Bit Assignments
Table 2-38. NVIC_ISPR Bit Assignments
BitsNameFunction
[31:0]SETPENDInterrupt set-pending bits.

Write:

0: No effect

1: Changes interrupt state to pending.

Read:

0: Interrupt is not pending

1: Interrupt is pending.

Important: Writing 1 to the NVIC_ISPR bit corresponding to:
  • An interrupt that is pending has no effect.
  • A disabled interrupt sets the state of that interrupt to pending.