12.2.4.1.3 Clock Out-Synchronous-Master Mode

The synchronous master mode is similar to the synchronous slave mode except that an external clock source (MMUART_X_SCK_IN), the receiver, and transmitter blocks use an internally generated synchronous clock which must be no greater than ½ APB clock frequency. The output clock, MMUART_X_SCK_OUT, is provided to the slave devices. The internally generated synchronous clock is set with the same baud rate divisor registers that are used in the Asynchronous mode. The Fractional baud rate generation mode should not be used in the Synchronous mode as the output clock can become unpredictable.

The MMUART_X_E_MST_SCK, master clock output enable (Table 12-1) is used for controlling a bi-directional pad that is used for MMUART_X_SCK_IN and MMUART_X_SCK_OUT. MMUART_X_E_MST_SCK=1 indicates master mode, forcing a bi-directional pad to be an output. Otherwise, the pad acts as input for MMUART_X_SCK_IN. MMUART_X_E_MST_SCK=1 indicates master mode, forcing a bi-directional pad to be an output. Otherwise, the pad acts as input for MMUART_X_SCK_IN.