12.2.4.1.1 Fractional Baud Rate Generation–Asynchronous Mode
The following figure depicts accumulative baud rate difference error in the Asynchronous mode. It also describes how fractional baud rate generation reduces this error by adding wait times, in the essence of forming a new average baud rate value that is between two given integer baud rate values.
Specifically, fractional baud rate generation modulates the integer baud rate with the integer baud rate + 1/16th of a Tbit time (bit transmit time) to yield a time averaged fractional value. The fractional resolution is 1/64th resolution. A 6-bit phase accumulator evenly distributes the fractional value over 64 Tbit times.
The following equation is used to calculate the fractional baud rate:
where,
APB_X_CLK: Input reference clock (APB_0_CLK for MMUART_0 and APB_1_CLK for MMUART_1)
DMR: Divisor latch for MSB
DLR: Divisor latch for LSB
DFR: Fractional divisor register
If a baud rate value of 1 and 1/64th (1.015625) is required, set the “DLR” to 1, the “DMR” to 0, and “DFR” to 1. Following examples illustrate the use of fractional baud rate.
The following figure describes the timing for a fractional baud rate value of 4.5. Exact averaging is accomplished in one Tbit (bit time) cycle.
- Lowest Common Denominator Value of 32 requires two Tbit times to complete the time modulation fractional baud rate. Lowest Common Denominator Value of 64 requires four Tbit times to complete the time averaged fractional baud rate. Thus, depending on the fraction chosen, the Tbit time may or may not be constant for 2 or 4 Tbit times max, but the time averaged Tbit time will be correct.
- Do not use the integer divisor value of 1 when in Fractional mode.
The following figure shows the timing for a fractional baud rate value of 2 and 3/64th. Exact averaging is accomplished in four Tbit cycles due to 64th granularity.
