12.2.4.1.2 Input Clock-Synchronous-Slave Mode

MMUART supports a synchronous master and slave mode. In the synchronous slave mode, the MMUART accepts an input clock that is synchronized to the data. The asynchronous state machine is harnessed to self-synchronize the start bit to a clock edge. With this circuit, the input clock can be positive-edge or negative-edge. The following figure shows the first edge that detects a start bit aligns the state machine to sample data on the next same edge.

In the synchronous slave mode, the Tx block does not output a clock or baud rate signal as it is assumed that the master provides clocking for any other slave peripherals. Additionally, the APB clock (APB_X_CLK) frequency must be at least 2x the input MMUART_X_SCK_IN (serial input synchronous clock) since MMUART_X_SCK_IN gets resynchronized.