4.2.4.2 Read Control

The following steps describe eNVM read control.

• The read transaction from the eNVM user array to AHBL bus uses the read data buffer as a mini cache.
• If the requested 32-bit word exists in the read data buffer, it will be returned immediately on the AHB bus; otherwise a 64-bit read access of the eNVM is initiated and will take several clock cycles as configured by Table 4-12 register.
• The eNVM data is stored in the read data buffer and provided to the AHB bus. Assuming that the eNVM address is incremented, the data value stored in the read data buffer is available for the next AHB read cycle.

The following figure shows the eNVM array read path.

The AHB Controller also supports WRAP4 burst operations, which are initiated by the cache controller. In this case, the AHB eNVM controller will automatically perform four 64-bit read operations (critical word first) and fill the read data buffer in advance to the AHB read transactions to increase system throughput.

In the eNVM array, the addresses are 64-bit locations; therefore each page of 1,024 bits (16 double words = 32 words) requires an AHBL address map, as specified in the following table.

When programming the eNVM, sector and page addresses must be programmed into the command (CMD) register, as specified in Table 4-6.