21.5.15 EDAC Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:7] | Reserved | 0 | |
| 6 | CAN_EDAC_EN | 0 | Allows the EDAC for CAN to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 5 | USB_EDAC_EN | 0 | Allows the EDAC for USB to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 4 | MAC_EDAC_RX_EN | 0 | Allows the EDAC for Ethernet Rx RAM to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 3 | MAC_EDAC_TX_EN | 0 | Allows the EDAC for Ethernet Tx RAM to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 2 | Reserved | 0 | |
| 1 | ESRAM1_EDAC_EN | 0 | Allows the EDAC for eSRAM1 to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 0 | ESRAM0_EDAC_EN | 0 | Allows the EDAC for eSRAM0 to be disabled. Allowed values: 0: Disabled 1: Enabled |