21.5.102 Clear EDAC Counters

Table 21-111. CLR_EDAC_COUNTERS
Bit Number	Name	Description
[31:14]	Reserved	—
13	CAN_EDAC_CNTCLR_2E	Pulse generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the CAN_EDAC_CNT register.
12	CAN_EDAC_CNTCLR_1E	Pulse generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the CAN_EDAC_CNT register.
11	USB_EDAC_CNTCLR_2E	Pulse generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the USB_EDAC_CNT register.
10	USB_EDAC_CNTCLR_1E	Pulse generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the USB_EDAC_CNT register.
9	MAC_EDAC_RX_CNTCLR_2E	Pulse generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the MAC_EDAC_RX_CNT register.
8	MAC_EDAC_RX_CNTCLR_1E	Pulse generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the MAC_EDAC_RX_CNT register.
7	MAC_EDAC_TX_CNTCLR_2E	Pulse generated to clear the 16-bit counter value in Ethernet MAC Tx RAM corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the MAC_EDAC_TX_CNT register.
6	MAC_EDAC_TX_CNTCLR_1E	Pulse generated to clear the 16-bit counter value in Ethernet MAC Tx RAM corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the MAC_EDAC_TX_CNT register.
5	Reserved
4	Reserved
3	ESRAM1_EDAC_CNTCLR_2E	Pulse generated to clear the 16-bit counter value in eSRAM1 corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the eSRAM1_EDAC_CNT register.
2	ESRAM1_EDAC_CNTCLR_1E	Pulse generated to clear the 16-bit counter value in eSRAM1 corresponding to count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the eSRAM1_EDAC_CNT register.
1	ESRAM0_EDAC_CNTCLR_2E	Pulse generated to clear the 16-bit counter value in eSRAM0 corresponding to count value of EDAC 2bit Errors. This in turn clears the upper 16 bits of eSRAM0_EDAC_CNT register.
0	ESRAM0_EDAC_CNTCLR_1E	Pulse generated to clear the 16-bit counter value in eSRAM0 corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the ESRAM0_EDAC_CNT register.

[31:14]

Reserved

0

—

13

CAN_EDAC_CNTCLR_2E

0

Pulse generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the CAN_EDAC_CNT register.

12

CAN_EDAC_CNTCLR_1E

0

Pulse generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the CAN_EDAC_CNT register.

11

USB_EDAC_CNTCLR_2E

0

Pulse generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the USB_EDAC_CNT register.

10

USB_EDAC_CNTCLR_1E

0

Pulse generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the USB_EDAC_CNT register.

9

MAC_EDAC_RX_CNTCLR_2E

0

Pulse generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the MAC_EDAC_RX_CNT register.

8

MAC_EDAC_RX_CNTCLR_1E

0

Pulse generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the MAC_EDAC_RX_CNT register.

7

MAC_EDAC_TX_CNTCLR_2E

0

Pulse generated to clear the 16-bit counter value in Ethernet MAC Tx RAM corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the MAC_EDAC_TX_CNT register.

6

MAC_EDAC_TX_CNTCLR_1E

0

Pulse generated to clear the 16-bit counter value in Ethernet MAC Tx RAM corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the MAC_EDAC_TX_CNT register.

5

Reserved

0

4

Reserved

0

3

ESRAM1_EDAC_CNTCLR_2E

0

Pulse generated to clear the 16-bit counter value in eSRAM1 corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the eSRAM1_EDAC_CNT register.

2

ESRAM1_EDAC_CNTCLR_1E

0

Pulse generated to clear the 16-bit counter value in eSRAM1 corresponding to count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the eSRAM1_EDAC_CNT register.

1

ESRAM0_EDAC_CNTCLR_2E

0

Pulse generated to clear the 16-bit counter value in eSRAM0 corresponding to count value of EDAC 2bit Errors. This in turn clears the upper 16 bits of eSRAM0_EDAC_CNT register.

0

ESRAM0_EDAC_CNTCLR_1E

0

Pulse generated to clear the 16-bit counter value in eSRAM0 corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the ESRAM0_EDAC_CNT register.