21.5.30 EDAC Interrupt Enable Control Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:15] | Reserved | 0 | |
| 14 | MDDR_ECC_INT_EN | 0 | Allows the error EDAC for MDDR status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 13 | CAN_EDAC_2E_EN | 0 | Allows the 2-bit error EDAC for CAN status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 12 | CAN_EDAC_1E_EN | 0 | Allows the 1-bit error EDAC for CAN status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 11 | USB_EDAC_2E_EN | 0 | Allows the 2-bit error EDAC for USB status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 10 | USB_EDAC_1E_EN | 0 | Allows the 1-bit error EDAC for USB status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 9 | MAC_EDAC_RX_2E_EN | 0 | Allows the 2-bit error EDAC for Ethernet Rx RAM status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 8 | MAC_EDAC_RX_1E_EN | 0 | Allows the 1-bit error EDAC for Ethernet Rx RAM status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 7 | MAC_EDAC_TX_2E_EN | 0 | Allows the 2-bit error EDAC for Ethernet Tx RAM status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 6 | MAC_EDAC_TX_1E_EN | 0 | Allows the 1-bit error EDAC for Ethernet Tx RAM status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 5 | Reserved | 0 | |
| 4 | Reserved | 0 | |
| 3 | ESRAM1_EDAC_2E_EN | 0 | Allows the 2-bit error EDAC for eSRAM1 status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 2 | ESRAM1_EDAC_1E_EN | 0 | Allows the 1-bit error EDAC for eSRAM1 status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 1 | ESRAM0_EDAC_2E_EN | 0 | Allows the 2-bit error EDAC for eSRAM0 status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 0 | ESRAM0_EDAC_1E_EN | 0 | Allows the 1-bit error EDAC for eSRAM0 status update to be disabled. Allowed values: 0: Disabled 1: Enabled |
Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.