18.3.5 ADC n Software Trigger Request Register

Note: A software trigger for channel x is generated when the corresponding bit is set in this register. The software trigger must be selected for the channel in TRG1SRC (ADnCHxCON[4:0]) or TRG2SRC (ADnCHxCON[23:19]) bits.
Table 18-9. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
SSoftware settable bitnCore NumberxChannel number
Name: ADnSWTRG
Offset: 0x810, 0xA10

Bit 3130292827262524 
 CH[31:24]TRG 
Access W/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/R 
Reset 00000000 
Bit 2322212019181716 
 CH[23:16]TRG 
Access W/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/R 
Reset 00000000 
Bit 15141312111098 
 CH[15:8]TRG 
Access W/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/R 
Reset 00000000 
Bit 76543210 
 CH[7:0]TRG 
Access W/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/RW/HC/R 
Reset 00000000 

Bits 31:24 – CH[31:24]TRG Channel x Software Trigger Request bit

Bits 23:16 – CH[23:16]TRG Channel x Software Trigger Request bit

Bits 15:8 – CH[15:8]TRG Channel x Software Trigger Request bit

Bits 7:0 – CH[7:0]TRG Channel x Software Trigger Request bit