18.3.1 ADC n Control Register

Note:

Timing is approximate and dependent on the 32K oscillator accuracy. Changing this value during ADC operation may cause erratic recalibration timing.
Recovery from Standby mode requires 230 ADC clock cycles.
Set the ADON bit only after the ADC module has been configured. Changing ADC configuration bits when ADON = 1 will result in unpredictable behavior.

Table 18-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
S	Software settable bit	n	Core Number	x	Channel number

Name:	ADnCON
Offset:	0x800, 0xA00


Bit	31	30	29	28	27	26	25	24
	ADRDY	CALRDY	CALREQ	ACALEN	CALRATE[1:0]		OMODE[1:0]
Access	HS/HC/R	HS/HC/R	R/W/HC	R/W	R/W	R/W	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RPTCNT[5:0]						RESERVED	STNDBY
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	0	1	0	1	0


Bit	15	14	13	12	11	10	9	8
	ON					TSTLOCK		TSTEN
Access	R/W					R/S		R/W/C
Reset	0					0		0


Bit	7	6	5	4	3	2	1	0
		CALCNT[1:0]
Access		R/W	R/W
Reset		0	0

Bit 31 – ADRDY ADC Ready bit

The bit indicates that the ADC has been enabled and has completed its power-up and self-calibration process.

Value	Description
`1`	ADC is ready
`0`	ADC is off

Bit 30 – CALRDY Calibration Done bit

Value	Description
`1`	Calibration cycle has finished
`0`	Calibration was not started or is in progress

Bit 29 – CALREQ Software Calibration Cycle Request bit

Value	Description
`1`	Setting this bit executes the calibration cycle
`0`	Calibration cycle is not requested

Bit 28 – ACALEN This bit enables periodic ADC recalibration. The calibration cycles period is defined by CALRATE (ADnCON[27:26]) bits.

Value	Description
`1`	Periodic recalibration is enabled
`0`	Periodic recalibration is off

Bits 27:26 – CALRATE[1:0] Auto Recalibration Period bits ⁽¹⁾

Value	Description
11	Recalibration every 4096 seconds
10	Recalibrate every 1024 seconds
01	Recalibrate every 64 seconds
00	Recalibrate every second

Bits 25:24 – OMODE[1:0] ADC Operation Mode Status bits

Value	Description
1x	ADC is on
01	ADC is in standby mode
00	ADC is powered down

Bits 23:18 – RPTCNT[5:0] Conversion Repeat Timer Period bits

This timer can be used to generate ADC Triggers periodically by selecting the RPTCNT timer as a trigger source in TRG1SRC (ADnCHxCON[4:0]) or TRG2SRC (ADnCHxCON[23:19]) bits. This timer counts ADC clock cycles.

Value	Description
111111	64 ADC clock cycles between triggers
...
0000010	3 ADC clock cycles between triggers
000001	2 ADC clock cycles between triggers
000000	1 ADC clock cycle between triggers

Bit 17 – RESERVED

Bit 16 – STNDBY ADC Standby Enable bit⁽²⁾

Value	Description
1	ADC module is in a power reduced mode
0	ADC is in normal active mode

Bit 15 – ON ADC Enable bit⁽³⁾

Value	Description
1	ADC module is enabled
0	ADC module is disabled

Bit 10 – TSTLOCK TSTEN Lock bit

Value	Description
`1`	TSTEN bit cannot be set to `1` but can be cleared to `0`
`0`	TSTEN bit can be set to `1`

Bit 8 – TSTEN Test Mode Enable bit

In the test mode the result of a conversion for all channels is overwritten with a value from ADnDATAOVR register.

Value	Description
`1`	The test mode is enabled
`0`	The test mode is disabled

Bits 6:5 – CALCNT[1:0] ADC Idle Cycles Prior to Calibration bits

Value	Description
11	Wait for 16 activity free ADC clock cycles before initiating requested calibration
10	Wait for 8 activity free ADC clock cycles before initiating requested calibration
01	Wait for 4 activity free ADC clock cycles before initiating requested calibration
00	Wait for 2 activity free ADC clock cycles before initiating requested calibration