18.3.13 ADC 2 Channel x Data Result Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| S | Software settable bit | n | Core Number | x | Channel number |
| Name: | AD2CHxDATA |
| Offset: | 0xA18, 0xA30, 0xA48, 0xA60, 0xA78, 0xA90, 0xAA8, 0xAC0, 0xAD8, 0xAF0, 0xB08, 0xB20, 0xB38, 0xB50, 0xB68, 0xB80, 0xB98, 0xBB0, 0xBC8, 0xBE0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DATAx[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DATAx[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DATAx[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATAx[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |