18.3.6 ADC 1 Channel x Control Register
Note:
- These bits are used with
Oversampling mode only when MODE[1:0] bits = ‘
11’ and are ignored for all other sampling modes. - For the correct operation this bit must be used only for the triggers
TRG1SRC[4:0] = ’
00100’ – ‘11111’. - Early interrupts are only
available for single sample operations (MODE[1:0] bits =
‘
00’). Multi-sample operations ignore the EIEN bit and use normal interrupt timing. - Do not use early interrupt if using DMA transfers; the data might not be ready. The early interrupt is asserted at the start of sampling.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| S | Software settable bit | n | Core Number | x | Channel number |
| Name: | AD1CHxCON |
| Offset: | 0x814, 0x82C, 0x844, 0x85C, 0x874, 0x88C, 0x8A4, 0x8BC, 0x8D4, 0x8EC, 0x904, 0x91C, 0x934, 0x94C, 0x964, 0x97C, 0x994, 0x9AC, 0x9C4, 0x9DC |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MODE[1:0] | ACCNUM[1:0] | ACCBRST | ACCRO | TRG1POL | EIEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRG2SRC[4:0] | CMPMOD[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIFF | PINSEL[3:0] | LEFT | NINSEL[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMC[2:0] | TRG1SRC[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:30 – MODE[1:0] Sampling Mode Selection bits
| Value | Description |
|---|---|
| 11 | Oversampling of multiple samples defined by ACCNUM[1:0] bits. The first conversion is initiated by TRG1SRC[4:0] trigger and all other conversions are executed by TRG2SRC[4:0] trigger. |
| 10 | Integration of multiple samples defined by: CNTx[15:0] bits (ADnCHxCNT[15:0]). The first conversion is initiated by TRG1SRC[4:0] trigger and all other conversions are executed by TRG2SRC[4:0] trigger. |
| 01 | Window gated by TRG1SRC[4:0] source. In this mode the samples are accumulated when a signal selected by TRG1SRC[4:0] bits has an active level. All conversions are initiated by TRG2SRC[4:0] trigger. The number of conversions is limited by CNTx[15:0] bits (ADnCHxCNT[15:0]). |
| 00 | Single sample initiated by TRG1SRC[4:0] trigger |
Bits 29:28 – ACCNUM[1:0] Oversampling Mode Number of Samples Selection bits (1)
| Value | Description |
|---|---|
| 11 | 256 samples, 16 bits result in ADnCHxDATA register |
| 10 | 64 samples, 15 bits result in ADnCHxDATA register |
| 01 | 16 samples, 14 bits result in ADnCHxDATA register |
| 00 | 4 samples, 13 bits result in ADnCHxDATA register |
Bit 27 – ACCBRST Oversampling Burst Mode Enable bit (1)
| Value | Description |
|---|---|
| 1 | The oversampling is performed as a continuous non-interruptible burst, during which all other conversion requests are blocked out until the process is completed. |
| 0 | Oversampling can be interrupted by a high priority conversion request |
Bit 26 – ACCRO Accumulator Roll-Over Enable bit
| Value | Description |
|---|---|
| 1 | ADnDATAx accumulator is not cleared; it is allowed to roll-over |
| 0 | ADnDATAx accumulator is cleared at the end of a multi-sample sequence |
Bit 25 – TRG1POL Starting Trigger Polarity Selection bit (2)
| Value | Description |
|---|---|
| 1 | Active level of the signal selected by TRG1SRC[4:0] bits is low; a falling edge generates a conversion request |
| 0 | Active level of the signal selected by TRG1SRC[4:0] bits is high; a rising edge generates a conversion request |
Bit 24 – EIEN Early Interrupt Enable bit (3)
| Value | Description |
|---|---|
| 1 | Early interrupt is enabled |
| 0 | Normal interrupt timing |
Bits 23:19 – TRG2SRC[4:0] Multi-Sample Conversions Re-Trigger Source Selection bits
Bits 18:16 – CMPMOD[2:0] Comparison Criteria Selection bits
| Value | Description |
|---|---|
| 111-101 | Comparison disabled |
| 100 | Conversion result is less or equal to (≤) ADnCHxCMPLO register |
| 011 | Conversion result is greater than (>) ADnCHxCMPLO register |
| 010 | Conversion result is in bounds of (≥) ADnCHxCMPLO and (≤) ADnCHxCMPHI |
| 001 | Conversion result is out of bounds of (<) ADnCHxCMPLO or (>) ADnCHxCMPHI |
| 000 | Comparison disabled |
Bit 15 – DIFF Signed Result Format Enable bit
| Value | Description |
|---|---|
| 1 | Differential Input mode; data is output as signed (two’s complement) |
| 0 | Single-Ended Input mode; data is output as unsigned |
Bits 14:11 – PINSEL[3:0] Analog Positive Input Selection for ADC bits
| Value | Description |
|---|---|
| 1111 | ADxAN15 |
| ... | |
| 0001 | ADxAN1 |
| 0000 | ADxAN0 |
Bit 10 – LEFT Fractional Data Output Format Enable bit
| Value | Description |
|---|---|
| 1 | Result in ADnDATAx register is aligned to the left (in the fractional format) |
| 0 | Result in ADnDATAx register is aligned to the right |
Bits 9:8 – NINSEL[1:0] Negative Analog Input Selection bit
| Value | Description |
|---|---|
| 11 | ADxANN3 |
| 10 | ADxANN2 |
| 01 | ADxANN1 |
| 00 | Ground (VSS); single-ended mode |
Bits 7:5 – SAMC[2:0] Sampling Time Selection bits (times listed for 80 MHz TAD clock)
| Value | Description |
|---|---|
| 111 |
14.5 TAD (181.25 nS) |
| 110 |
12.5 TAD (156.25 nS) |
| 101 |
10.5 TAD (131.25 nS) |
| 100 | 8.5 TAD (106.25 nS) |
| 011 | 6.5 TAD ( 81.25 nS) |
| 010 |
4.5 TAD ( 56.25 nS) |
| 001 |
2.5 TAD ( 31.25 nS) |
| 000 | 0.5 TAD ( 6.25 nS) |