18.3.17 ADC 2 Channel x Secondary Accumulator Register

Table 18-21. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
S	Software settable bit	n	Core Number	x	Channel number

Name:	AD2CHxACC
Offset:	0xBC0, 0xBD8, 0xBF0


Bit	31	30	29	28	27	26	25	24
	ACC[31:24]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ACC[23:16]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ACC[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ACC[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – ACC[31:0] Secondary Accumulator

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