18.3.2 ADC n Test Mode Data Overwrite Register Table 18-6. Register Bit Attribute LegendSymbolDescriptionSymbolDescriptionSymbolDescriptionRReadable bitHCCleared by Hardware(Gray cell)UnimplementedWWritable bitHSSet by HardwareXBit is unknown at ResetCWrite to clearSSoftware settable bitxChannel number Name: ADnDATAOVROffset: 0x804, 0xA04Bit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 DATAOVR[11:8] Access R/WR/WR/WR/W Reset 0000 Bit 76543210 DATAOVR[7:0] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bits 11:0 – DATAOVR[11:0] Conversion Result Value in Test Mode bits
Bit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 DATAOVR[11:8] Access R/WR/WR/WR/W Reset 0000 Bit 76543210 DATAOVR[7:0] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000
