18.3.14 ADC 2 Channel x Counter Register

Table 18-18. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
S	Software settable bit	n	Core Number	x	Channel number

Name:	AD2CHxCNT
Offset:	0xA1C, 0xA34, 0xA4C, 0xA64, 0xA7C, 0xA94, 0xAAC, 0xAC4, 0xADC, 0xAF4, 0xB0C, 0xB24, 0xB3C, 0xB54, 0xB6C, 0xB84, 0xB9C, 0xBB4, 0xBCC, 0xBE4


Bit	31	30	29	28	27	26	25	24
	CNTSTAT[15:8]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CNTSTAT[7:0]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – CNTSTAT[15:0]

Number of conversions done in Integration (MODE[1:0] bits = ‘10’) and Window (MODE[1:0] bits = ‘01’) Sampling modes

Bits 15:0 – CNT[15:0]

Number of samples for an Integration Sampling mode (MODE[1:0] bits = ‘10’) and maximum number of samples for a Window Sampling mode (MODE[1:0] bits = ‘01’)