18.3.4 ADC n Comparators Status Register

Table 18-8. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
SSoftware settable bitnCore NumberxChannel number
Name: ADnCMPSTAT
Offset: 0x80C, 0xA0C

Note: These bits are set when ADC channel data meets comparison criteria and cleared when a “0” is written to this bit by software.

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     CMP[19:16]FLG 
Access HS/C/RHS/C/RHS/C/RHS/C/R 
Reset 0000 
Bit 15141312111098 
 CH[15:8]CMP 
Access HS/C/RHS/C/RHS/C/RHS/C/RHS/C/RHS/C/RHS/C/RHS/C/R 
Reset 00000000 
Bit 76543210 
 CH[7:0]CMP 
Access HS/C/RHS/C/RHS/C/RHS/C/RHS/C/RHS/C/RHS/C/RHS/C/R 
Reset 00000000 

Bits 19:16 – CMP[19:16]FLG Channel x Comparator Event Detection bit

Bits 15:8 – CH[15:8]CMP Channel x Comparator Event Detection bit

Bits 7:0 – CH[7:0]CMP Channel x Comparator Event Detection bit