17.3.20 PWM Generator x Phase Register
Note: This register cannot be modified while PGxSTAT.UPDATE =
1.
Table 17-26. Register Bit Attribute Legend| Symbol | Description | Symbol | Description | Symbol | Description |
|---|
| R | Readable
bit | HC | Cleared by
Hardware | (Gray
cell) | Unimplemented |
| W | Writable
bit | HS | Set by
Hardware | X | Bit is unknown
at Reset |
| C | Write to
clear | S | Software
settable bit | x | Channel
number |
| Name: | PGxPHASE |
| Offset: | 0x1074, 0x10BC, 0x1104,
0x114C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | PHASE[19:16] | |
| Access | | | | | R/W | R/W | R/W | R/W | |
| Reset | | | | | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | PHASE[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | PHASE[7:4] | Reserved[3:0] | |
| Access | R/W | R/W | R/W | R/W | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 19:16 – PHASE[19:16] PWM Generator x Phase
Register
Bits 15:8 – PHASE[15:8] PWM Generator x Phase Register
Bits 7:4 – PHASE[7:4] PWM Generator x Phase Register
Bits 3:0 – Reserved[3:0]
