17.3.4 Master Phase Register

Table 17-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	MPHASE
Offset:	0x100C

Bits 19:16 – MPHASE[19:16] Master Phase Register

This register holds the phase offset value that can be shared by multiple PWM Generators.

This register holds the phase offset value that can be shared by multiple PWM Generators.

This register holds the phase offset value that can be shared by multiple PWM Generators.