17.3.12 PWM Generator x Status Register

Table 17-18. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: PGxSTAT
Offset: 0x1054, 0x109C, 0x10E4, 0x112C

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 SEVTFLTEVTCLEVTFFEVTSACTFLTACTCLACTFFACT 
Access HS/CHS/CHS/CHS/CRRRR 
Reset 00000000 
Bit 76543210 
 TRSETTRCLRCAPUPDATEUPDREQSTEERCAHALFTRIG 
Access WWR/HSRWRRR 
Reset 00000000 

Bit 15 – SEVT PCI Sync Event

ValueDescription
1

A PCI Sync event has occurred (rising edge on PCI Sync output or PCI Sync output is high when module is enabled)

0

No PCI Sync event has occurred

Bit 14 – FLTEVT PCI Fault Active Status

ValueDescription
1

A Fault event has occurred (rising edge on PCI Fault output or PCI Fault output is high when module is enabled)

0

No Fault event has occurred

Bit 13 – CLEVT PCI Current Limit Status

ValueDescription
1

A PCI current limit event has occurred (rising edge on PCI current limit output or PCI current limit output is high when module is enabled)

0

No PCI current limit event has occurred

Bit 12 – FFEVT PCI Feed-Forward Active Status

ValueDescription
1

A PCI feed-forward event has occurred (the rising edge on the PCI feed-forward output or PCI feed-forward output is high when module is enabled)

0

No PCI feed-forward event has occurred

Bit 11 – SACT PCI Sync Status

ValueDescription
1

PCI Sync output is active

0

PCI Sync output is inactive

Bit 10 – FLTACT PCI Fault Active Status

ValueDescription
1

PCI Fault output is active

0

PCI Fault output is inactive

Bit 9 – CLACT PCI Current Limit Status

ValueDescription
1

PCI current limit output is active

0

PCI current limit output is inactive

Bit 8 – FFACT PCI Feed-Forward Active Status

ValueDescription
1

PCI feed-forward output is active

0

PCI feed-forward output is inactive

Bit 7 – TRSET PWM Generator Software Trigger Set

User software writes a ‘1’ to this bit location to trigger a PWM Generator cycle. The bit location always reads as ‘0’. The TRIG bit will indicate ‘1’ when the PWM Generator is triggered.

Bit 6 – TRCLR PWM Generator Software Trigger Clear

User software writes a ‘1’ to this bit location to stop a PWM Generator cycle. The bit location always reads as ‘0’. The TRIG bit will indicate ‘0’ when the PWM Generator is not triggered.

Bit 5 – CAP Capture Status

ValueDescription
1

PWM Generator time base value has been captured in PGxCAP

0

No capture has occurred

Bit 4 – UPDATE PWM Data Register Update Status/Control

ValueDescription
1

PWM Data register update is pending – user Data registers are not writable

0

No PWM Data register update is pending

Bit 3 – UPDREQ PWM Data Register Update Request

User software writes a ‘1’ to this bit location to request a PWM Data register update. The bit location always reads as ‘0’. The UPDATE status bit will indicate a ‘1’ when an update is pending.

Bit 2 – STEER Output Steering Status (Push-Pull Output mode only)

ValueDescription
1

PWM Generator is in 2nd cycle of Push-Pull mode

0

PWM Generator is in 1st cycle of Push-Pull mode

Bit 1 – CAHALF Half Cycle Status (Center-Aligned modes only)

ValueDescription
1

PWM Generator is in 2nd half of time base cycle

0

PWM Generator is in 1st half of time base cycle

Bit 0 – TRIG Trigger Status

ValueDescription
1

PWM Generator is triggered and PWM cycle is in progress

0

No PWM cycle is in progress