17.3.14 PWM Generator x Event Register

Note:

Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
This source can optionally be used as a PCI input, PCI qualifier, PCI terminator or PCI terminator qualifier.

Table 17-20. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PGxEVT
Offset:	0x105C, 0x10A4, 0x10EC, 0x1134


Bit	31	30	29	28	27	26	25	24
	FLTIEN	CLIEN	FFIEN	SIEN			IEVTSEL[1:0]
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			0	0


Bit	23	22	21	20	19	18	17	16
	ADTR2EN3	ADTR2EN2	ADTR2EN1	ADTR1OFS[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADTR1PS[4:0]					ADTR1EN3	ADTR1EN2	ADTR1EN1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PWMPCI[2:0]			UPDTRG[1:0]		PGTRGSEL[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – FLTIEN PCI Fault Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI Fault active signal.

Value	Description
`1`	Fault interrupt is enabled
`0`	Fault interrupt is disabled

Bit 30 – CLIEN PCI Current Limit Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI current limit active signal.

Value	Description
`1`	Current limit interrupt is enabled
`0`	Current limit interrupt is disabled

Bit 29 – FFIEN PCI Feed-Forward Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI feed-forward active signal.

Value	Description
`1`	Feed-forward interrupt is enabled
`0`	Feed-forward interrupt is disabled

Bit 28 – SIEN PCI Sync Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI Sync active signal.

Value	Description
`1`	Sync interrupt is enabled
`0`	Sync interrupt is disabled

Bits 25:24 – IEVTSEL[1:0] Interrupt Event Selection⁽¹⁾

Value	Description
`11`	Time base interrupts are disabled (Sync, Fault, current limit and feed-forward events can be independently enabled)
`10`	Interrupts CPU at ADC Trigger 1 event
`01`	Interrupts CPU at TRIGA compare event
`00`	Interrupts CPU at EOC

Bit 23 – ADTR2EN3 ADC Trigger 2 Source is PGxTRIGC Compare Event Enable⁽¹⁾

Value	Description
`1`	PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 2
`0`	PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 2

Bit 22 – ADTR2EN2 ADC Trigger 2 Source is PGxTRIGB Compare Event Enable⁽¹⁾

Value	Description
`1`	PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 2
`0`	PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 2

Bit 21 – ADTR2EN1 ADC Trigger 2 Source is PGxTRIGA Compare Event Enable⁽¹⁾

Value	Description
`1`	PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 2
`0`	PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 2

Bits 20:16 – ADTR1OFS[4:0] ADC Trigger 1 Offset Selection⁽¹⁾

Value	Description
`11111`	Offset by 31 trigger events
`. . .`	`. . .`
`00010`	Offset by 2 trigger events
`00001`	Offset by 1 trigger event
`00000`	No offset

Bits 15:11 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection⁽¹⁾

Value	Description
`11111`	1:32
`. . .`	`. . .`
`00010`	1:3
`00001`	1:2
`00000`	1:1

Bit 10 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable⁽¹⁾

Value	Description
`1`	PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 1
`0`	PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 1

Bit 9 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable⁽¹⁾

Value	Description
`1`	PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 1
`0`	PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 1

Bit 8 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable⁽¹⁾

Value	Description
`1`	PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 1
`0`	PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 1

Bits 7:5 – PWMPCI[2:0] PWM PCI Source Selection⁽²⁾

See Table 17-6 for device-specific PWM output selection for PCI signal.

Value	Description
111	PWM Generator #8 output used as PCI signal
110	PWM Generator #7 output used as PCI signal
101	PWM Generator #6 output used as PCI signal
100	PWM Generator #5 output used as PCI signal
011	PWM Generator #4 output used as PCI signal
010	PWM Generator #3 output used as PCI signal
001	PWM Generator #2 output used as PCI signal
000	PWM Generator #1 output used as PCI signal

Bits 4:3 – UPDTRG[1:0] Update Trigger Select⁽¹⁾

Value	Description
`11`	A write of the PGxTRIGA register automatically sets the UPDREQ bit
`10`	A write of the PGxPHASE register automatically sets the UPDREQ bit
`01`	A write of the PGxDC register automatically sets the UPDREQ bit
`00`	User must set the UPDREQ bit (PGxSTAT[3]) manually

Bits 2:0 – PGTRGSEL[2:0] PWM Generator Trigger Output Selection⁽¹⁾

Note: These events are derived from the internal PWM Generator time base comparison events.

Value	Description
`111`	Reserved
`110`	Reserved
`101`	Reserved
`100`	Reserved
`011`	PGxTRIGC compare event is the PWM Generator trigger
`010`	PGxTRIGB compare event is the PWM Generator trigger
`001`	PGxTRIGA compare event is the PWM Generator trigger
`000`	EOC event is the PWM Generator trigger

17.3.14 PWM Generator x Event Register

Bit 31 – FLTIEN PCI Fault Interrupt Enable

Bit 30 – CLIEN PCI Current Limit Interrupt Enable

Bit 29 – FFIEN PCI Feed-Forward Interrupt Enable

Bit 28 – SIEN PCI Sync Interrupt Enable

Bits 25:24 – IEVTSEL[1:0] Interrupt Event Selection(1)

Bit 23 – ADTR2EN3 ADC Trigger 2 Source is PGxTRIGC Compare Event Enable(1)

Bit 22 – ADTR2EN2 ADC Trigger 2 Source is PGxTRIGB Compare Event Enable(1)

Bit 21 – ADTR2EN1 ADC Trigger 2 Source is PGxTRIGA Compare Event Enable(1)

Bits 20:16 – ADTR1OFS[4:0] ADC Trigger 1 Offset Selection(1)

Bits 15:11 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection(1)

Bit 10 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable(1)

Bit 9 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable(1)

Bit 8 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable(1)

Bits 7:5 – PWMPCI[2:0] PWM PCI Source Selection(2)

Bits 4:3 – UPDTRG[1:0] Update Trigger Select(1)

Bits 2:0 – PGTRGSEL[2:0] PWM Generator Trigger Output Selection(1)