17.3.19 PWM Generator x Leading-Edge Blanking Register

Caution should be exercised when modifying this register while PGxCON.ON = 1; unexpected results may occur.

Table 17-25. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PGxLEB
Offset:	0x1070, 0x10B8, 0x1100, 0x1148


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					PHR	PHF	PLR	PLF
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	LEB[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	LEB[7:4]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0

Bit 19 – PHR PWMx Rising Edge Trigger Enable bit

Value	Description
`1`	Rising edge of PWMx will trigger the LEB duration counter
`0`	LEB ignores the rising edge of PWMx

Bit 18 – PHF PWMxH Falling Edge Trigger Enable bit

Value	Description
`1`	Falling edge of PWMx will trigger the LEB duration counter
`0`	LEB ignores the falling edge of PWMx

Bit 17 – PLR PWMx Rising Edge Trigger Enable bit

Value	Description
`1`	Rising edge of PWMx will trigger the LEB duration counter
`0`	LEB ignores the rising edge of PWMx

Bit 16 – PLF PWMx Falling Edge Trigger Enable bit

Value	Description
`1`	Falling edge of PWMx will trigger the LEB duration counter
`0`	LEB ignores the falling edge of PWMx

Bits 15:8 – LEB[15:8] Leading-Edge Blanking Period bits

These bits select the leading edge blanking period. The 4 LSbs of the blanking time are not implemented, providing a blanking resolution of TPWMCLK. The LEB period is (LEB[15:4]+1)*TPWMCLK. The minimum blanking period is 5, values 0,1,2,3,4 all get LEB period of 5*TPWMCLK.