17.3.28 PWM Generator x Capture Register

Table 17-34. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					CAP[19:16]
Access					R	R	R	R
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CAP[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CAP[7:4]
Access	R	R	R	R
Reset	0	0	0	0

Bits 19:16 – CAP[19:16] PGx Time Base Capture

PGx Time Base Capture bits.

Note: A capture event can be manually initiated in software by writing a ‘1’ to PGxCAP[0].

The CAP bit (PGxSTAT[5]) will indicate when a new capture value is available. A read of PGxCAP will automatically clear the CAP bit and allow a new capture event to occur. PGxCAP[3:0] will always read as ‘0’.

Bits 15:8 – CAP[15:8] PGx Time Base Capture

PGx Time Base Capture bits.

Note: A capture event can be manually initiated in software by writing a ‘1’ to PGxCAP[0].

The CAP bit (PGxSTAT[5]) will indicate when a new capture value is available. A read of PGxCAP will automatically clear the CAP bit and allow a new capture event to occur. PGxCAP[3:0] will always read as ‘0’.

Bits 7:4 – CAP[7:4] PGx Time Base Capture

PGx Time Base Capture bits.

Note: A capture event can be manually initiated in software by writing a ‘1’ to PGxCAP[0].

The CAP bit (PGxSTAT[5]) will indicate when a new capture value is available. A read of PGxCAP will automatically clear the CAP bit and allow a new capture event to occur. PGxCAP[3:0] will always read as ‘0’.

Name:	PGxCAP
Offset:	0x1094, 0x10DC, 0x1124, 0x116C