17.3.9 Combinatorial PWM Logic Control Register y

Note: ‘y’ denotes a common instance (A-F); the number of the available combinatorial PWM logic is device-dependent.

Table 17-15. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	LOGCONy
Offset:	0x1020, 0x1024, 0x1028, 0x102C, 0x1030, 0x1034


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	PWMS1y[3:0]				PWMS2y[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	S1yPOL	S2yPOL	PWMLFy[1:0]			PWMLFyD[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0

Bits 15:12 – PWMS1y[3:0] Combinatorial PWM Logic Source #1 Selection

See Table 17-4 for device-specific selections.

Note: Logic function input will be connected to ‘0’ if the PWM channel is not present.

Bits 11:8 – PWMS2y[3:0] Combinatorial PWM Logic Source #2 Selection

See Table 17-4 for device-specific selections.

Note: Logic function input will be connected to ‘0’ if the PWM channel is not present.

Bit 7 – S1yPOL Combinatorial PWM Logic Source #1 Polarity

Value	Description
`1`	Input is inverted
`0`	Input is positive logic

Bit 6 – S2yPOL Combinatorial PWM Logic Source #2 Polarity

Value	Description
`1`	Input is inverted
`0`	Input is positive logic

Bits 5:4 – PWMLFy[1:0] Combinatorial PWM Logic Function Selection

Value	Description
`11`	Reserved
`10`	PWMS1y ^ PWMS2y (XOR)
`01`	PWMS1y & PWMS2y (AND)
`00`	PWMS1y \| PWMS2y (OR)

Bits 2:0 – PWMLFyD[2:0] Combinatorial PWM Logic Destination Selection

See Table 17-5 for device-specific selections.

Note: Instances of y = A, C, E of LOGCONy assign logic function output to the PWMxH pin. Instances of y = B, D, F of LOGCONy assign logic function to the PWMxL pin.