17.3.18 PWM Generator Sync PCI(1)
- Caution should be exercised when modifying this register while PGxCON.ON = 1; unexpected results may occur.
- This bit has no effect when the
SWTERM control bit is used as the PCI Termination Event or if TERM[2:0] <
‘
101’.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PGxSPCI |
| Offset: | 0x106C, 0x10B4, 0x10FC, 0x1144 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BPEN | BPSEL[2:0] | TERMPS | ACP[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SWPCI | SWPCIM[1:0] | LATMOD | TQPS | TQSS[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TSYNCDIS | TERM[2:0] | AQPS | AQSS[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWTERM | PSYNC | PPS | PSS[4:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – BPEN PCI Bypass Enable
| Value | Description |
|---|---|
1 | PCI function is enabled and local PCI logic is bypassed; PWM Generator will be controlled by PCI function in the PWM Generator selected by the BPSEL[2:0] bits |
0 | PCI function is not bypassed |
Bits 30:28 – BPSEL[2:0] PCI Bypass Source Selection
0’ if the selected PWM
Generator is not present.Bit 27 – TERMPS PCI Termination Polarity Select bit
| Value | Description |
|---|---|
1 | Inverted |
0 | Not inverted |
Bits 26:24 – ACP[2:0] PCI Acceptance Criteria Selection
- Do not use this selection when the TERM[2:0] bits (PGxyPCI[14:12]) are set to auto-termination.
| Value | Description |
|---|---|
| 111 | Reserved |
| 110 | Reserved |
| 101 | Latched any edge(1) |
| 100 | Latched rising edge |
| 011 | Latched |
| 010 | Any edge |
| 001 | Rising edge |
| 000 | Level-sensitive |
Bit 23 – SWPCI Software PCI Control
| Value | Description |
|---|---|
1 | Drives a ‘ |
0 | Drives a ‘ |
Bits 22:21 – SWPCIM[1:0] Software PCI Control Mode
| Value | Description |
|---|---|
11 | Reserved |
10 | SWPCI bit is assigned to termination qualifier logic |
01 | SWPCI bit is assigned to acceptance qualifier logic |
00 | SWPCI bit is assigned to PCI acceptance logic |
Bit 20 – LATMOD PCI SR Latch Mode
| Value | Description |
|---|---|
1 | SR latch is Reset-dominant in Latched Acceptance modes |
0 | SR latch is set-dominant in Latched Acceptance modes |
Bit 19 – TQPS Termination Qualifier Polarity Select
| Value | Description |
|---|---|
1 | Inverted |
0 | Not inverted |
Bits 18:16 – TQSS[2:0] Termination Qualifier Source Selection
- Polarity control bit, TQPS, has no effect on these selections.
| Value | Description |
|---|---|
111 | SWPCI control bit only (qualifier forced to
‘ |
110 | Selects PCI Source #9 |
101 | Selects PCI Source #8 |
100 | Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits) |
011 | PWM Generator is triggered |
010 | LEB is active |
001 | Duty cycle is active (base PWM Generator signal) |
000 | No termination qualifier used (qualifier forced to
‘ |
Bit 15 – TSYNCDIS Termination Synchronization Disable
| Value | Description |
|---|---|
1 |
Termination of latched PCI occurs immediately |
0 |
Termination of latched PCI occurs at PWM EOC |
Bits 14:12 – TERM[2:0] Termination Event Selection
- PCI sources are device-dependent.
- Do not use this selection when the ACP[2:0] bits (PGxyPCI[26:24]) are set for latched on any edge.
| Value | Description |
|---|---|
111 |
Selects PCI Source #9(1) |
110 |
Selects PCI Source #8(1) |
101 |
Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits) |
100 |
PGxTRIGC trigger event |
011 |
PGxTRIGB trigger event |
010 |
PGxTRIGA trigger event |
001 |
Auto-Terminate: Terminate when PCI source transitions from active to inactive(2) |
000 |
Manual Terminate: Terminate on a write of
‘ |
Bit 11 – AQPS Acceptance Qualifier Polarity Select
| Value | Description |
|---|---|
1 |
Inverted |
0 |
Not inverted |
Bits 10:8 – AQSS[2:0] Acceptance Qualifier Source Selection
| Value | Description |
|---|---|
111 |
SWPCI control bit only (qualifier forced to
‘ |
110 |
Selects PCI Source #9 |
101 |
Selects PCI Source #8 |
100 |
Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits) |
011 |
PWM Generator is triggered |
010 |
LEB is active |
001 |
Duty cycle is active (base PWM Generator signal) |
000 |
No acceptance qualifier is used (qualifier forced to
‘ |
Bit 7 – SWTERM PCI Software Termination
A write of ‘1’ to this location will produce a
termination event. This bit location always reads as ‘0’.
Bit 6 – PSYNC PCI Synchronization Control
| Value | Description |
|---|---|
1 |
PCI source is synchronized to PWM EOC |
0 |
PCI source is not synchronized to PWM EOC |
Bit 5 – PPS PCI Polarity Select
| Value | Description |
|---|---|
1 |
Inverted |
0 |
Not inverted |