17.3.10 PWM Event Output Control Register y

Note: ‘y’ denotes a common instance (A-F); the number of the available combinatorial PWM logic is  device-dependent.

Table 17-16. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PWMEVTy
Offset:	0x1038, 0x103C, 0x1040, 0x1044, 0x1048, 0x104C

Bit 15 – EVTyOEN PWM Event Output Enable

Value	Description
`1`	Event output signal is output on the PWMEy pin
`0`	Event output signal is internal only

Value	Description
`1`	Event output signal is active-low
`0`	Event output signal is active-high

Note: The event signal is stretched using peripheral_clk because different PWM Generators may be operating from different clock sources.

Value	Description
`1`	Event output signal pulse width is not stretched
`0`	Event output signal is stretched to eight PWM clock cycles minimum

Event output signal pulse will be synchronized to peripheral_clk.

Value	Description
`1`	Event output signal is synchronized to the system clock
`0`	Event output is not synchronized to the system clock

Note: This is the PWM Generator output signal prior to Output mode logic and any output override logic.

Value	Description
`1111-1010`	Reserved
`1001`	ADC Trigger 2 signal
`1000`	ADC Trigger 1 signal
`0111`	STEER signal (available in Push-Pull Output modes only)
`0110`	CAHALF signal (available in Center-Aligned modes only)
`0101`	PCI Fault active output signal
`0100`	PCI current limit active output signal
`0011`	PCI feed-forward active output signal
`0010`	PCI Sync active output signal
`0001`	PWM Generator output signal⁽¹⁾
`0000`	Source is selected by the PGTRGSEL[2:0] bits

See Table 17-6 for device-specific selections.

Note: No event will be produced if the selected PWM Generator is not present.