17.3.13 PWM Generator x I/O Control Register
- This bit(s) cannot be modified while PGxCON.ON = 1.
- This bit(s) cannot be modified while PCLKCON.LOCK = 1. Otherwise, caution should be exercised when modifying this bit when PGxCON.ON = 1; unexpected results may occur.
- This bit(s) cannot be modified while UPDATE = 1.
- Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PGxIOCON |
| Offset: | 0x1058, 0x10A0, 0x10E8, 0x1130 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CAPSRC[2:0] | PPSEN | DTCMPSEL | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PMOD[1:0] | PENH | PENL | POLH | POLL | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CLMOD | SWAP | OVRENH | OVRENL | OVRDAT[1:0] | OSYNC[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTDAT[1:0] | CLDAT[1:0] | FFDAT[1:0] | DBDAT[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 30:28 – CAPSRC[2:0] Time Base Capture Source Selection
1’ to
PGxCAP[0].| Value | Description |
|---|---|
111 | Reserved |
110 | Reserved |
101 | Reserved |
100 | Capture time base value at assertion of selected PCI Fault signal |
011 | Capture time base value at assertion of selected PCI Current Limit signal |
010 | Capture time base value at assertion of selected PCI Feed-Forward signal |
001 | Capture time base value at assertion of selected PCI Sync signal |
000 | No hardware source selected for time base capture – software only |
Bit 25 – PPSEN Peripheral Pin Select Enable bit(4)
| Value | Description |
|---|---|
1 | Peripheral pin select enabled |
0 | Peripheral pin select disabled, as a result, PWM outputs are hard-mapped to pins |
Bit 24 – DTCMPSEL Dead-Time Compensation Select(4)
| Value | Description |
|---|---|
1 | Dead-time compensation is controlled by PCI feed-forward limit logic |
0 | Dead-time compensation is controlled by PCI Sync logic |
Bits 21:20 – PMOD[1:0] PWM Generator Output Mode Selection(2)
| Value | Description |
|---|---|
11 | Reserved |
10 | PWM Generator outputs operate in Push-Pull mode |
01 | PWM Generator outputs operate in Independent mode |
00 | PWM Generator outputs operate in Complementary mode |
Bit 19 – PENH PWMxH Output Port Enable(2)
| Value | Description |
|---|---|
1 | PWM Generator controls the PWMxH output pin |
0 | PWM Generator does not control the PWMxH output pin |
Bit 18 – PENL PWMxL Output Port Enable(2)
| Value | Description |
|---|---|
1 | PWM Generator controls the PWMxL output pin |
0 | PWM Generator does not control the PWMxL output pin |
Bit 17 – POLH PWMxH Output Polarity(2)
| Value | Description |
|---|---|
1 | Output pin is active-low |
0 | Output pin is active-high |
Bit 16 – POLL PWMxL Output Polarity(2)
| Value | Description |
|---|---|
1 | Output pin is active-low |
0 | Output pin is active-high |
Bit 15 – CLMOD Current Limit Mode Select
| Value | Description |
|---|---|
1 |
If PCI current limit is active, then the PWMxH and PWMxL output signals are inverted (bit flipping), and the CLDAT[1:0] bits are not used |
0 |
If PCI current limit is active, then the CLDAT[1:0] bits define the PWM output levels |
Bit 14 – SWAP Swap PWM Signals to PWMxH and PWMxL Device Pins
| Value | Description |
|---|---|
1 |
The PWMxH signal is connected to the PWMxL pin and the PWMxL signal is connected to the PWMxH pin |
0 |
PWMxH/L signals are mapped to their respective pins |
Bit 13 – OVRENH User Override Enable for PWMxH Pin
| Value | Description |
|---|---|
1 |
OVRDAT[1] provides data for output on the PWMxH pin |
0 |
PWM Generator provides data for the PWMxH pin |
Bit 12 – OVRENL User Override Enable for PWMxL Pin
| Value | Description |
|---|---|
1 |
OVRDAT[0] provides data for output on the PWMxL pin |
0 |
PWM Generator provides data for the PWMxL pin |
Bits 11:10 – OVRDAT[1:0] Data for PWMxH/PWMxL Pins if Override is Enabled
| Description |
|---|
|
If OVRENH = |
|
If OVRENL = |
Bits 9:8 – OSYNC[1:0] User Output Override Synchronization Control
| Value | Description |
|---|---|
11 | User output
overrides via the SWAP, OVRENL/H, and OVRDAT[1:0] bits are synchronized to the
data buffer update of the selected PWM mode. This makes this setting equivalent to
setting 10 when UPDMOD[2:0] = 000 with UPDREQ
properly set manually. |
10 |
User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur when specified by the UPMOD[2:0] bits in the PGxCON register. |
01 |
User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur immediately (as soon as possible). |
00 |
User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits are synchronized to the local PWM time base (next start of cycle). |
Bits 7:6 – FLTDAT[1:0] Data for PWMxH/PWMxL Pins if FLT Event is Active
| Description |
|---|
|
If Fault is active, then FLTDAT[1] provides data for PWMxH |
|
If Fault is active, then FLTDAT[0] provides data for PWMxL |
Bits 5:4 – CLDAT[1:0] Data for PWMxH/PWMxL Pins if CLMT Event is Active
| Description |
|---|
|
If current limit is active, then CLDAT[1] provides data for PWMxH |
|
If current limit is active, then CLDAT[0] provides data for PWMxL |
Bits 3:2 – FFDAT[1:0] Data for PWMxH/PWMxL Pins if Feed-Forward Event is Active
| Description |
|---|
|
If feed-forward is active, then FFDAT[1] provides data for PWMxH |
|
If feed-forward is active, then FFDAT[0] provides data for PWMxL |
Bits 1:0 – DBDAT[1:0] Data for PWMxH/PWMxL Pins if Debug Mode is Active
| Description |
|---|
|
If Debug mode is active and PTFRZ = |
|
If Debug mode is active and PTFRZ = |