Introduction
1 Definitions, Acronyms and Abbreviations
2 Overall Description
3 Metrology Interface Definition
- 3.1 Metrology Control Registers
  - 3.1.1 Metrology State Control
    Metrology State Control
  - 3.1.2 Metrology Feature Control Register
    Metrology Feature Control Register
  - 3.1.3 AFE Selection
    AFE Selection
  - 3.1.4 Channel Matrix Register
    Channel Matrix Register
  - 3.1.5 Harmonic Control Register
    Harmonic Control Register
  - 3.1.6 Meter Type Settings Register
    Meter Type Settings Register
  - 3.1.7 Number of Line Cycles for Integration Period
    Number of Line Cycles for Integration Period
  - 3.1.8 Max Number of Samples in an Integration Period
    Max Number of Samples in an Integration Period
  - 3.1.9 Pulse Control Register x (x = 0, 1, 2)
    Pulse Control Register x (x = 0, 1, 2)
  - 3.1.10 Pulse Meter Constant Register x (x = 0, 1, 2)
    Pulse Meter Constant Register x (x = 0, 1, 2)
  - 3.1.11 Synthesizer Address
    Synthesizer Address
  - 3.1.12 Creep Threshold for Active Energy
    Creep Threshold for Active Energy
  - 3.1.13 Per-Phase Creep Threshold for Active Energy
    Per-Phase Creep Threshold for Active Energy
  - 3.1.14 Creep Threshold for Quadergy
    Creep Threshold for Quadergy
  - 3.1.15 Per-Phase Creep Threshold for Reactive Energy
    Per-Phase Creep Threshold for Reactive Energy
  - 3.1.16 Creep Threshold of Phase Current
    Creep Threshold of Phase Current
  - 3.1.17 Per-Phase Creep Threshold of Phase Current
    Per-Phase Creep Threshold of Phase Current
  - 3.1.18 Creep Threshold for Apparent Energy
    Creep Threshold for Apparent Energy
  - 3.1.19 Power Offset Control Register
    Power Offset Control Register
  - 3.1.20 Active Power Offset Register
    Active Power Offset Register
  - 3.1.21 Reactive Power Offset Register
    Reactive Power Offset Register
  - 3.1.22 Apparent Power Offset Register
    Apparent Power Offset Register
  - 3.1.23 Voltage Swell Threshold
    Voltage Swell Threshold
  - 3.1.24 Voltage Sag Threshold
    Voltage Sag Threshold
  - 3.1.25 Voltage Interrupt Thresholds
    Voltage Interrupt Thresholds
  - 3.1.26 Current Conversion Factor
    Current Conversion Factor
  - 3.1.27 Voltage Conversion Factor
    Voltage Conversion Factor
  - 3.1.28 Current Channel Magnitude Calibration Constants
    Current Channel Magnitude Calibration Constants
  - 3.1.29 Voltage Channel Magnitude Calibration Constants
    Voltage Channel Magnitude Calibration Constants
  - 3.1.30 Per-Channel Phase Calibration Constants
    Per-Channel Phase Calibration Constants
  - 3.1.31 Waveform Capture Control Register
    Waveform Capture Control Register
  - 3.1.32 Capture Buffer Size
    Capture Buffer Size
  - 3.1.33 Waveform Capture Destination Buffer Address
    Waveform Capture Destination Buffer Address
  - 3.1.34 AFE Control 0 Register (For ATSENSE203/301)
    AFE Control 0 Register (For ATSENSE203/301)
  - 3.1.35 AFE Control 0 Register (For MCP3912/13/14)
    AFE Control 0 Register (For MCP3912/13/14)
  - 3.1.36 Per-Phase Active Power Offset Register
    Per-Phase Active Power Offset Register
  - 3.1.37 Per-Phase Reactive Power Offset Register
    Per-Phase Reactive Power Offset Register
- 3.2 Metrology Status Registers
- 3.3 Accumulated Output Quantities
- 3.4 Per-Cycle Accumulated Output Quantities
- 3.5 Harmonic Analysis Output Quantities
- 3.6 Derived Output Quantities
4 Interface between Metrology and Application
5 Annex – Meter Forms
The service type determines what meter form is being implemented and how the Metrology DSP core interprets and processes the ADC values.
6 References
7 Revision History
Microchip Information

3.1.22 Apparent Power Offset Register

The parameter POWER_OFFSET_S represents the total squared current (Amp²-hour/cycle) offset per full cycle (20 ms for 50 Hz, 16.667 ms for 60 Hz). This offset is subtracted from the current value used to calculate the apparent power:

S = Vrms * (Irms – POWER_OFFSET_S).

Two alternative usage examples are given below.

To achieve the accurate result, measure an apparent power load curve with the apparent power offset disabled, follow these steps:
1. Mathematically calculate the current offset causing the measured errors, in mA.
2. Convert this value to the units of POWER_OFFSET_S, for example:
  1. The current RMS causing the errors is 21 mA.
  2. K_I = 617.284.
  3. Frequency is 50 Hz, resulting in 80 samples per cycle.
  4. POWER_OFFSET_S = 80 * 2⁴⁰ * (0.021 / 617.284)² = 101802.
For a faster computation, use the accumulators I_A, I_B, and I_C, follow these steps:
1. Apply the nominal voltage to the meter and set the current to zero.
2. Read the I_A, I_B, and I_C accumulators and compute the average. For improved accuracy, take multiple measurements or increase the integration period.
3. Calculate the corresponding value for a single cycle, for example:
  1. I_A = 52687391, I_B = 39070069, I_C = 47225301.
  2. I_Average = 46327587.
  3. Samples accumulated = 40000 (approximately 10 seconds).
  4. Samples in 1 cycle = 80 (50 Hz).
  5. POWER_OFFSET_S = 46327587 * 80 / 40000 = 92655.

This register can be used with pulse types 6 (S) and 7 (S_F). However, it must not be used with pulse type 8. For pulse type 8 the per-phase active and reactive power offsets must be used.

POWER_OFFSET_S is stored in the sQ1.30 format and it is applied to each full cycle. POWER_OFFSET_S affects only S and S_F pulse generation and ACC_Tx pulse accumulators.

Refer to the “PIC32CXMTx Metrology User Guide” (DS50003460) for additional information.

Name:	POWER_OFFSET_S
Property:	Read-Write

This value affects the apparent power offset of appointed pulse.


Bit	31	30	29	28	27	26	25	24
	POWER_OFFSET_S[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	POWER_OFFSET_S[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	POWER_OFFSET_S[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	POWER_OFFSET_S[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – POWER_OFFSET_S[31:0] (sQ1.30)

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