Introduction
1 Definitions, Acronyms and Abbreviations
2 Overall Description
3 Metrology Interface Definition
- 3.1 Metrology Control Registers
  - 3.1.1 Metrology State Control
    Metrology State Control
  - 3.1.2 Metrology Feature Control Register
    Metrology Feature Control Register
  - 3.1.3 AFE Selection
    AFE Selection
  - 3.1.4 Channel Matrix Register
    Channel Matrix Register
  - 3.1.5 Harmonic Control Register
    Harmonic Control Register
  - 3.1.6 Meter Type Settings Register
    Meter Type Settings Register
  - 3.1.7 Number of Line Cycles for Integration Period
    Number of Line Cycles for Integration Period
  - 3.1.8 Max Number of Samples in an Integration Period
    Max Number of Samples in an Integration Period
  - 3.1.9 Pulse Control Register x (x = 0, 1, 2)
    Pulse Control Register x (x = 0, 1, 2)
  - 3.1.10 Pulse Meter Constant Register x (x = 0, 1, 2)
    Pulse Meter Constant Register x (x = 0, 1, 2)
  - 3.1.11 Synthesizer Address
    Synthesizer Address
  - 3.1.12 Creep Threshold for Active Energy
    Creep Threshold for Active Energy
  - 3.1.13 Per-Phase Creep Threshold for Active Energy
    Per-Phase Creep Threshold for Active Energy
  - 3.1.14 Creep Threshold for Quadergy
    Creep Threshold for Quadergy
  - 3.1.15 Per-Phase Creep Threshold for Reactive Energy
    Per-Phase Creep Threshold for Reactive Energy
  - 3.1.16 Creep Threshold of Phase Current
    Creep Threshold of Phase Current
  - 3.1.17 Per-Phase Creep Threshold of Phase Current
    Per-Phase Creep Threshold of Phase Current
  - 3.1.18 Creep Threshold for Apparent Energy
    Creep Threshold for Apparent Energy
  - 3.1.19 Power Offset Control Register
    Power Offset Control Register
  - 3.1.20 Active Power Offset Register
    Active Power Offset Register
  - 3.1.21 Reactive Power Offset Register
    Reactive Power Offset Register
  - 3.1.22 Apparent Power Offset Register
    Apparent Power Offset Register
  - 3.1.23 Voltage Swell Threshold
    Voltage Swell Threshold
  - 3.1.24 Voltage Sag Threshold
    Voltage Sag Threshold
  - 3.1.25 Voltage Interrupt Thresholds
    Voltage Interrupt Thresholds
  - 3.1.26 Current Conversion Factor
    Current Conversion Factor
  - 3.1.27 Voltage Conversion Factor
    Voltage Conversion Factor
  - 3.1.28 Current Channel Magnitude Calibration Constants
    Current Channel Magnitude Calibration Constants
  - 3.1.29 Voltage Channel Magnitude Calibration Constants
    Voltage Channel Magnitude Calibration Constants
  - 3.1.30 Per-Channel Phase Calibration Constants
    Per-Channel Phase Calibration Constants
  - 3.1.31 Waveform Capture Control Register
    Waveform Capture Control Register
  - 3.1.32 Capture Buffer Size
    Capture Buffer Size
  - 3.1.33 Waveform Capture Destination Buffer Address
    Waveform Capture Destination Buffer Address
  - 3.1.34 AFE Control 0 Register (For ATSENSE203/301)
    AFE Control 0 Register (For ATSENSE203/301)
  - 3.1.35 AFE Control 0 Register (For MCP3912/13/14)
    AFE Control 0 Register (For MCP3912/13/14)
  - 3.1.36 Per-Phase Active Power Offset Register
    Per-Phase Active Power Offset Register
  - 3.1.37 Per-Phase Reactive Power Offset Register
    Per-Phase Reactive Power Offset Register
- 3.2 Metrology Status Registers
- 3.3 Accumulated Output Quantities
- 3.4 Per-Cycle Accumulated Output Quantities
- 3.5 Harmonic Analysis Output Quantities
- 3.6 Derived Output Quantities
4 Interface between Metrology and Application
5 Annex – Meter Forms
The service type determines what meter form is being implemented and how the Metrology DSP core interprets and processes the ADC values.
6 References
7 Revision History
Microchip Information

3.1.24 Voltage Sag Threshold

For each half-cycle of the dominant phase, the RMS values of all voltages are calculated, taking into account both the fundamental and harmonic components. Each calculated value is then compared to the corresponding SAG_THRESHOLD_Vx, (where x = [A, B, C]), to assess whether a voltage sag condition is present. For each half cycle that a voltage sag exists, the associated flag, SAG_DET_Vx is set to 1.

A threshold is allowed for each phase and is computed using the native phase voltages, before transformation to implied 4WY service. This allows setting different thresholds for non-balanced service types.

The SAG_THRESHOLD_Vx is stored in the uQ0.32 format, therefore, set the threshold value as follows:

Name:	SAG_THRESHOLD_Vx
Property:	Read-Write


Bit	31	30	29	28	27	26	25	24
	SAG_THRESHOLD_Vx[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SAG_THRESHOLD_Vx[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	SAG_THRESHOLD_Vx[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SAG_THRESHOLD_Vx[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – SAG_THRESHOLD_Vx[31:0] (uQ0.32)

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.